The abstract of Japanese Patent application laid open No. 2000-124749 discloses an amplifier circuit that includes a gate bias stage for supplying a gate voltage to an amplifying transistor.
FIG. 1 schematically shows the prior art amplifier circuit. The amplifier circuit comprises an amplifier stage 10 and a bias stage 12. The amplifier stage serves to amplify high frequency signals, for example in the Gigahertz range. Typically, this requires various high frequency coupling and blocking elements etc. However, as the invention is mainly concerned with biasing, these have been omitted from the figures for the sake of clarity.
The amplifier stage has an input 100, which is coupled to the gate of an amplifier transistor 104 via a coupling capacitor 102. The drain of amplifier transistor 104 is coupled to a positive power supply connection V+ via a load circuit 108. The drain also forms the output 106 of the amplifier circuit.
For achieving of high frequency stability and gain the source of the amplifier transistor 104 is coupled directly to a ground power supply connection (gnd). This means that a careful control of the bias voltage (average DC voltage) at its gate is required to ensure required amplification properties. Relatively small errors in the bias voltage can have substantial effects on amplification. Amplifier transistor 104 is of the “normally on” type (depletion type), which is in a conductive state its gate-source voltage is zero. Hence, a negative bias voltage (outside the range of the drain-source voltages on the same side of that range as the source voltage) is required.
The bias stage 12 is provided to feed the DC bias voltage to the gate of the amplifier transistor 104. Because amplifier transistor 104 is of the normally on type, a negative power supply connection V− is needed for the bias stage 12, to produce a bias voltage below ground voltage. The bias stage 12 comprises a bias transistor 120 with a gate coupled to the negative power supply connection V−, a source coupled to the negative power supply connection V− via a source resistor 122 and a drain coupled to ground (gnd) via a drain resistor 124. The drain of bias transistor 120 is coupled to the gate of amplifier transistor 104 via a high frequency blocking circuit 126 (e.g. a resistor).
Current through bias transistor 120 causes a voltage drop across drain resistor 124, which defines the bias voltage for amplifier transistor 104. The bias stage 12 of the prior art amplifier circuit is designed to compensate for threshold voltage deviations of amplifier transistor 104. Such deviations can be the result of temperature fluctuations or (to a lesser extent) of manufacturing spread for example. The idea is to use a bias transistor 120 that will exhibit the same deviations as amplifier transistor 104 and to arrange bias stage 12 to convert the deviations of the threshold voltage of its bias transistor 120 into a gate voltage for the amplifier transistor 104 so that the difference between that gate voltage and the threshold voltage is independent of the deviations.
A threshold voltage deviation of bias transistor 120 can be modelled as an opposite change in an input voltage source at the gate of bias transistor 120. The bias stage 12 is arranged to amplify its input voltage change with an amplification gain “g” of minus one, so that the threshold voltage deviation is reproduced at the gate of amplifier transistor 104. The gain “g” of bias stage 12, is determined by (1) the resistance value Rd of drain resistor 124, (2) the transconductance “s” of bias transistor 120 (in the expression Id=s(Vgate−Vsource−Va) for the drain current Id of bias transistor 120 as a function of its gate and source voltage and its threshold voltage Va) and (3) the resistance value Rs of source resistor 122. In an approximationg=−Rd/(Rq+1/s)Hence for g=−1 it holds approximately that Rd=Rq+1/s. This ensures that threshold voltage deviations are compensated.
However, for many applications the bias voltage is too negative, when full compensation of threshold voltage fluctuation is achieved, causing amplifier transistor 104 to pinch off. This is because the voltage drop across drain resistor 124 Rd is bigger than the voltage drop across source resistor 122, since Rd>Rs (this in contrast to the response to voltage changes which is equal for the voltages across both resistors). Therefore it is desirable to add a positive offset in the voltage across drain resistor 124. Typically, this involves adding a component between the drain resistor 124 and the positive power supply connection V+. However, it has been found that this introduces an undesirable positive power supply voltage sensitivity that is hard to suppress.
A further problem that may arise for some transistors is negative power supply voltage sensitivity. This sensitivity arises when the drain of bias transistor 120 does not act as a perfect current source, so that changes in the level of the negative power supply affects the current from the drain and thereby the bias voltage.